Department of Electrical Engineering
Rebecca Park received her BS from Cornell University, and is currently a PhD candidate in Electrical Engineering at Stanford University, under the supervision of Professor H.-S. Philip Wong and co-advised by Professor Subhasish Mitra. Her current research interest is in the development of high-performance and energy-efficient nanoelectronics, in which she has focused on carbon nanotube-based FETs. Rebecca is a recipient of the Intel/SRCEA Masters Scholarship (2014-2016) and the Intel/SRCEA PhD Fellowship (2016-2019). She was a teaching assistant for EE 21N, “What is Nanotechnology?” (2016, 2017, and 2018 winter), where she taught undergraduate students how to fabricate silicon transistors in the cleanroom. She has also interned at IBM (2017 summer), and will be interning at Apple (2018 summer).Device Technology for Energy-Efficient Carbon Nanotube Transistors
Advancements through scaling of silicon-based transistors is becoming increasingly challenging. As a result, alternative technologies are being explored. Carbon nanotube (CNT) is a potential channel material for future technology due to its one-dimensional, ultra-thin body, which minimizes short-channel effects while maintaining high mobility and carrier velocity. Therefore, carbon nanotube field-effect transistors (CNFETs) promise to enable energy-efficient and highperformance digital very-large-scale integration (VLSI) logic circuits.
However, several challenges must be overcome before realizing CNT as a practical technology. Due to an absence of standard methodology to characterize hysteresis in CNFETs, understanding the root cause of – and developing a method to reduce – hysteresis has been challenging. A pulsed-measurement technique has been developed to quantify traps responsible for hysteresis in transistors made of low-dimensional channel materials, such as CNT and MoS2. By leveraging a physics-based model of the charge trapping process, a source of traps unique to lowdimensional channels has been discovered. This understanding enabled the demonstration of a VLSI-compatible method to reduce CNFET hysteresis.
Additionally, CNFETs with low parasitic capacitances must be developed to fulfill the energyefficiency benefits projected. CNFETs in previous studies generally had large parasitic capacitances between the gate and the source/drain metals (CGS, CGD). A separation between the metal contacts is necessary to lower the capacitance, but comes at a cost of increased resistance in un-gated regions. CNFET structures with reduced capacitance while maintaining low resistance require heavy doping at the un-gated region, which can substantially reduce the parasitics for improved energy-efficiency.