Ching-Hua Fiona Wang
Department of Electrical Engineering
Fiona Ching-Hua Wang received her Master's degree in Electronic Engineering from the National Tsing-Hua University in 2009. She then participated in the 20 nm CMOS frontend R&D group at TSMC for two years. She is now studying for her PhD in the Electrical Engineering Department at Stanford University under the direction of Professor Philip H-S Wong. She has worked on Nonvolatile Memory (NVM) in the Ya-Chin King and Chrong-Jung Lin research group before 2014 and published at IEDM (2010 and 2013) and won the Taiwanese Government Scholarship for PhD program. Her PhD research has focused on the development of 2D material applications for transistors and memory. She won best in session on SRC Techcon 2017 with her work on Scandium contacts to black phosphorus. She is currently working on hetero-structure 2D materials for memory application, including 2D transistor switching 2D RRAM in 1T1R structure and a 2D material based selector.2D Materials for CMOS and Memory Integration
Modern CPU performance is reaching a plateau due to the scaling limitations of transistor technology. Additionally, the data transmission time between CPU and memory (i.e. memory wall) has become a significant limitation as data usage has expanded exponentially, requiring future computer technology to directly integrate memory and transistor devices. Layered two-dimensional (2D) materials have attracted attention due to their intrinsically thin body that is preferable for transistor scaling. Also, the weak inter-layer boding allows for low-temperature transfer processing which is suitable for 3D CPU integration. In my thesis, I first studied the high-mobility 2D material black phosphorous (BP) transistors with different metals contacts. My work achieved unipolar n-type BP transistors with ultra-low work function metals, demonstrating record high n-type current. Furthermore, the study revealed the physical mechanisms of controlling doping and de-pinning effects for n- and p- type BP transistors. I have also implemented a 3D monolithic two-level 1 transistors/1 resistor structures for memory arrays with a complete 2D material system, using hexagonal-Boron Nitride (hBN) as a memory cell and monolayer Molybdenum Disulfide (MoS2) as the transistor selector. In order to further increase memory array density, I am currently developing a two-terminal selector utilizing a 2D material heterostructure with a H-shape band diagram. This design can lower the off-state current while maintaining a high on-state tunneling current density by virtue of atomic thinness of 2D material. Due to the transferable feature of 2D material, the process can be easily integrated for monolithic 3D CPUs, overcoming the “memory wall”.